Electrical circuits today function in many modes. Two of these modes are the ECL mode and the CMOS mode. A single substrate or chip will have only one of these modes and when fast high density circuits are desired the CMOS mode will be used because of its lower power consumption. However, a complex circuit or system may be designed so that signals from one mode interfaces with circuitry constructed using the other mode. This presents a problem in that the ECL on-off (1-0) states are represented by negative 0.95 volts and negative 1.71 volts, respectively. The CMOS standard on-off (1-0) states, however, are plus 5 volts and 0 volts, respectively. Thus, one problem that is immediately clear is that the CMOS circuit does not require and usually does not have negative voltage available.
A converter circuit, then, is necessary for signals which must pass between ECL and CMOS in either direction. Because of the extremely high speeds which are now being demanded, any such conversion circuit must be extremely fast acting and must not introduce any errors into the circuitry. This later is particularly difficult to achieve when it is remembered that the nominal electrical characteristics of this type of electrical circuitry are subject to temperature variations. Sometimes, these variations are steep and because of the relative slight difference between the 1 and 0 voltage states, these variations can cause significant errors if not compensated for properly.
While there are some previous circuits that performed this type of function, typically they do not translate from voltage levels that are below ground to voltage levels above ground. In this regard, they take their ECL circuit and instead of running it from a negative supply which is typical for ECL circuits, they run it from a positive supply, thereby shifting their ECL levels up by 5 volts to create a pseudo ECL level. This is not available in some situations, and thus some circuits designed desire to keep the ECL voltage levels separate from the CMOS voltage levels.
Simply putting both a negative and a positive voltage supply on the BiCMOS chip would be relatively straightforward to do. However, there is a basic problem in that these high speed types of processes would be subject to breakdown problems if both a positive and a negative supply were on the same chip. This occurs since the voltage potential is greater than the junctions can withstand. Thus, CMOS circuits thrive much better in an environment with only positive 5 volts available, measured from ground (0 volts). At the same time it is important to have the true ECL negative voltage levels available for communicating back and forth between ECL and CMOS circuits.
Thus, there exists a need for a high speed ECL to CMOS conversion circuit built into a CMOS circuit which will accept the negative ECL signal levels and convert those levels to the standard positive signal levels recognized by the CMOS circuit all without introducing negative voltages onto the CMOS chip and all without sacrificing speed of operation so that speeds in the order of 0.5 nanosecond are possible.
There is a further need in the art for a CMOS circuit which functions from ECL logic levels without requiring negative voltage levels to be available within the CMOS circuit and which allows for internal testing of the CMOS circuit.